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Time-Triggered Ethernet (AS6802/TTE)

Overview

Time-Triggered Ethernet (TTE) standardized as SAE AS6802 extends IEEE 802.3 Ethernet with deterministic, fault-tolerant clock synchronization and time-triggered traffic scheduling. TTE enables mixed-criticality networking where safety-critical time-triggered traffic coexists with standard Ethernet traffic on the same physical infrastructure.

Key Facts

  • Standard: SAE AS6802 (2011), TTTech implementation
  • Wire speed: 100 Mbps / 1 Gbps standard Ethernet
  • Traffic classes: Time-Triggered (TT), Rate-Constrained (RC), Best-Effort (BE)
  • Sync precision: < 1 µs across the network
  • Fault tolerance: Byzantine fault-tolerant clock sync
  • Usage: NASA Orion, Boeing 787, TTTech deterministic networks, ESA

Deterministic Ethernet Architecture

The Problem with Standard Ethernet

Standard Ethernet provides no timing guarantees frames can be delayed arbitrarily by collisions, buffering, and best-effort forwarding. TTE solves this by adding:

  1. Global time base All nodes share a synchronized clock (< 1 µs precision)
  2. Offline schedule Time-triggered frames are dispatched at pre-computed times
  3. Traffic policing Switches enforce bandwidth contracts per traffic class
Standard Ethernet:        TTE Network:

  ┌──?──?──?──┐           ┌──────────────────────┐
  │ Frame may  │           │ TT: Arrives at EXACT │
  │ arrive     │           │     scheduled time   │
  │ anytime    │           │ RC: Bounded latency  │
  │ (0-∞ ms)  │           │ BE: Fair share of    │
  └────────────┘           │     remaining BW     │
                           └──────────────────────┘

Three Traffic Classes

Traffic Class Hierarchy

graph TD
    A[Ethernet Frame Arrives] --> B{Traffic Class?}
    B -->|EtherType 0x891D<br>+ schedule match| C[Time-Triggered TT]
    B -->|EtherType 0x891D<br>+ BAG constraint| D[Rate-Constrained RC]
    B -->|Standard frame| E[Best-Effort BE]

    C --> F[Dispatch at exact<br>scheduled time]
    D --> G[Forward within<br>BAG window]
    E --> H[Forward when<br>TT/RC idle]

    style C fill:#4a4,stroke:#333,color:#fff
    style D fill:#fa0,stroke:#333
    style E fill:#aaa,stroke:#333

Comparison Table

Property Time-Triggered (TT) Rate-Constrained (RC) Best-Effort (BE)
Determinism Exact time (scheduled) Bounded latency No guarantee
Jitter < 1 µs Bounded by BAG Unbounded
Bandwidth Reserved (guaranteed) Policed (max rate) Remaining
Configuration Offline schedule table BAG + max frame size None
Fault tolerance Byzantine tolerant Leak-rate limiting Drop on overload
Use case Flight control, sensor fusion Engine data, cabin Maintenance, updates
Priority Highest (preempts all) Medium Lowest
EtherType 0x891D 0x891D Standard

Bandwidth Allocation Gap (BAG)

Rate-Constrained traffic uses the BAG concept (shared with ARINC 664/AFDX):

BAG = Minimum inter-frame interval

  Frame    BAG     Frame    BAG     Frame
  ├───┤←─────────→├───┤←─────────→├───┤
  │ RC│           │ RC│           │ RC│
  └───┘           └───┘           └───┘
  t=0     t=BAG    t=2×BAG

BAG values: 1, 2, 4, 8, 16, 32, 64, 128 ms
Max bandwidth = frame_size / BAG

BAG vs AFDX

TTE's RC traffic class is functionally equivalent to AFDX (ARINC 664p7) Virtual Links. The BAG mechanism and policing rules are identical TTE extends AFDX with the addition of TT traffic class and global synchronization.

Protocol Control Frames (PCF)

PCF Structure

Clock synchronization uses Protocol Control Frames special Ethernet frames exchanged between switches and end systems:

PCF Frame (64 bytes minimum)
┌────────────┬────────────┬──────────┬────────────┬─────────────────┐
│ Dst MAC    │ Src MAC    │EtherType │ PCF Header │    Payload      │
│ (6 bytes)  │ (6 bytes)  │ (2: 891D)│ (28 bytes) │  (≥22 bytes)    │
└────────────┴────────────┴──────────┴────────────┴─────────────────┘

PCF Header Fields

Field Size Description
Integration Cycle 4 bytes Current synchronization round
Membership New 4 bytes Bitmask of active sync members
Sync Priority 2 bytes Priority for leader election
Sync Domain 1 byte Synchronization domain ID
Type 1 byte PCF type (see below)
Transparent Clock 8 bytes Accumulated residence time
Cluster Time 8 bytes Synchronized cluster timestamp

PCF Types

Type Name Direction Purpose
0 CS_REQUEST End System → Switch Request integration
1 CS_RESPONSE Switch → End System Acknowledge integration
2 CA_FRAME Switch ↔ Switch Compression agreement
3 IN_FRAME Switch → End Systems Integration frame (time broadcast)
4 COLDSTART Sync Master → All Initial time establishment

Clock Synchronization

State Machine

stateDiagram-v2
    [*] --> UNSYNC: Power on
    UNSYNC --> SYNC: Received valid IN_FRAME<br>from compression master
    SYNC --> STABLE: N consecutive successful<br>sync rounds (N=3 typical)
    STABLE --> STABLE: Continuous sync<br>(integration cycle repeats)
    STABLE --> SYNC: Missed sync round<br>(1 cycle)
    SYNC --> UNSYNC: Missed M consecutive<br>sync rounds (M=5 typical)
    UNSYNC --> COLDSTART_INIT: Sync master timeout<br>(no IN_FRAMEs received)
    COLDSTART_INIT --> SYNC: Became sync master<br>(sent COLDSTART PCF)

Synchronization Sequence

Integration Cycle (typical 10ms):

Time ──────────────────────────────────────────────────►

End System A:  ──── CS_REQUEST ────────────────────────►
End System B:  ──── CS_REQUEST ────────────────────────►
Switch (CM):       ◄─────┘ Compress timestamps
                    ├──── CA_FRAME ──── (to other switches)
                    └──── IN_FRAME ──── (to all end systems)
End System A:  ◄──────────────┘ Adjust local clock
End System B:  ◄──────────────┘ Adjust local clock

                    Sync precision: < 1 µs achieved

Transparent Clock

TTE switches implement transparent clocking each switch adds its frame residence time to the PCF's transparent clock field:

End System → Switch 1 → Switch 2 → End System
              (+3.2µs)    (+2.8µs)

Transparent Clock value: 6.0µs (accumulated)

Receiving end system compensates:
  actual_send_time = receive_time - transparent_clock_value

Byzantine Fault Tolerance

TTE uses a compression function in switches. Multiple sync masters send CS_REQUESTs; the switch computes the median timestamp. This tolerates up to f Byzantine-faulty sync masters in a system with 3f+1 masters.

Schedule Table

Offline Configuration

TT traffic is dispatched according to a pre-computed schedule table loaded at system startup:

// Schedule table entry
typedef struct {
    uint32_t cycle_offset_ns;    // Offset within integration cycle
    uint16_t ct_id;              // Critical Traffic ID
    uint8_t  port;               // Egress port
    uint16_t frame_size;         // Expected frame size
    uint8_t  period_multiple;    // Dispatch period = N × integration cycle
} tte_schedule_entry_t;

Example schedule (10ms integration cycle):

Offset CT ID Port Size Period Description
0.5 ms 100 1 64 B 1× (10ms) Flight control command
1.0 ms 101 2 128 B 1× (10ms) Sensor fusion data
3.0 ms 200 1 256 B 2× (20ms) Navigation update
5.0 ms 300 3 512 B 10× (100ms) Display refresh

Integration Cycle

The integration cycle is the fundamental time period of TTE operation:

Integration Cycle (e.g., 10ms)
┌─────────────────────────────────────────────────────────────┐
│  Sync Phase  │         Data Phase                            │
│  (PCF xchg)  │  TT frames dispatched per schedule table     │
│  ~500µs      │  RC frames forwarded within BAG              │
│              │  BE frames fill remaining bandwidth           │
├──────────────┼─────────┬─────────┬────────┬────────┬────────┤
│ PCF exchange │  TT#100 │  TT#101 │ RC/BE  │ TT#200 │ RC/BE  │
│              │  @0.5ms │  @1.0ms │  fill  │  @3.0ms│  fill  │
└──────────────┴─────────┴─────────┴────────┴────────┴────────┘

API Reference

Core Types

#include "tte.h"

typedef enum {
    TTE_TRAFFIC_TT = 0,     // Time-Triggered
    TTE_TRAFFIC_RC = 1,     // Rate-Constrained
    TTE_TRAFFIC_BE = 2      // Best-Effort
} tte_traffic_class_t;

typedef enum {
    TTE_SYNC_UNSYNC = 0,
    TTE_SYNC_INTEGRATING = 1,
    TTE_SYNC_SYNC = 2,
    TTE_SYNC_STABLE = 3
} tte_sync_state_t;

typedef struct {
    uint8_t  dst_mac[6];
    uint8_t  src_mac[6];
    uint16_t ethertype;          // 0x891D for TTE
    uint32_t integration_cycle;
    uint32_t membership_new;
    uint16_t sync_priority;
    uint8_t  sync_domain;
    uint8_t  pcf_type;
    int64_t  transparent_clock;  // Nanoseconds
    int64_t  cluster_time;       // Nanoseconds
} tte_pcf_t;

typedef struct {
    uint32_t ct_id;              // Critical Traffic identifier
    uint32_t cycle_offset_ns;   // Dispatch offset
    uint8_t  period_multiple;   // Period = N × integration cycle
    uint16_t max_frame_size;
    uint8_t  egress_port;
} tte_schedule_entry_t;

typedef struct {
    tte_schedule_entry_t *entries;
    size_t                entry_count;
    uint32_t              integration_cycle_ns;
} tte_schedule_t;

Switch Functions

// Initialize TTE switch context
void tte_switch_init(tte_switch_t *sw, uint8_t num_ports,
                     const tte_schedule_t *schedule);

// Process incoming frame; returns traffic class and action
tte_traffic_class_t tte_switch_classify(const tte_switch_t *sw,
                                         const uint8_t *frame,
                                         size_t frame_len);

// Forward TT frame according to schedule (called by timer)
int tte_switch_dispatch_tt(tte_switch_t *sw, uint32_t current_time_ns);

// Forward RC frame (checks BAG compliance)
int tte_switch_forward_rc(tte_switch_t *sw, const uint8_t *frame,
                          size_t frame_len, uint8_t ingress_port);

// Update transparent clock field in PCF
void tte_switch_update_transparent_clock(tte_pcf_t *pcf,
                                          uint32_t residence_ns);

End System Functions

// Initialize TTE end system
void tte_es_init(tte_end_system_t *es, const tte_schedule_t *schedule);

// Clock synchronization: process received IN_FRAME
void tte_es_process_pcf(tte_end_system_t *es, const tte_pcf_t *pcf);

// Get current sync state
tte_sync_state_t tte_es_get_sync_state(const tte_end_system_t *es);

// Get synchronized network time
int64_t tte_es_get_time(const tte_end_system_t *es);

// Send TT frame (must be called at scheduled offset)
int tte_es_send_tt(tte_end_system_t *es, uint32_t ct_id,
                   const uint8_t *payload, size_t len);

// Send RC frame (BAG-policed)
int tte_es_send_rc(tte_end_system_t *es, uint16_t vl_id,
                   const uint8_t *payload, size_t len);

Compression Master Functions

// Initialize compression master (runs on switch)
void tte_cm_init(tte_compression_master_t *cm, uint8_t num_sync_masters,
                 uint32_t integration_cycle_ns);

// Feed incoming CS_REQUEST; returns true when compression complete
bool tte_cm_process_cs_request(tte_compression_master_t *cm,
                               uint8_t sender_id, int64_t timestamp);

// Get compressed timestamp (median of received CS_REQUESTs)
int64_t tte_cm_get_compressed_time(const tte_compression_master_t *cm);

// Generate IN_FRAME for broadcast
void tte_cm_generate_in_frame(tte_compression_master_t *cm, tte_pcf_t *pcf);

Usage in Avionics & Aerospace

Platform Role Configuration
NASA Orion MPCV Crew vehicle data network TTE backbone, 16 end systems
Boeing 787 Network backbone TTE + AFDX hybrid
TTTech Nerve Industrial edge computing TTE deterministic layer
ESA launchers Avionics network TTE for GNC data
Airbus Helicopters Flight control network TTE with A664 interop

TTE vs AFDX (ARINC 664p7)

AFDX provides rate-constrained networking (bounded latency). TTE adds time-triggered scheduling with sub-µs synchronization. Many modern avionics networks use both: TTE for the most critical flows (flight control) and AFDX/RC for less time-sensitive data.

Build & Run

make -C src/network/tte
./build/tte_demo

Output:

=== Time-Triggered Ethernet (AS6802) Demo ===
Integration cycle: 10ms | Sync masters: 3 | End systems: 4

--- Clock Synchronization ---
[UNSYNC] Waiting for IN_FRAME...
[SYNC]   Received IN_FRAME from CM, adjusting clock: +23ns
[SYNC]   Round 2: clock correction: -8ns
[STABLE] 3 consecutive successful rounds STABLE

--- Schedule Table ---
  CT 100 @ offset  0.5ms (every  10ms) → port 1 [Flight Control]
  CT 101 @ offset  1.0ms (every  10ms) → port 2 [Sensor Fusion]
  CT 200 @ offset  3.0ms (every  20ms) → port 1 [Navigation]
  CT 300 @ offset  5.0ms (every 100ms) → port 3 [Display]

--- Traffic Classification ---
  Frame 0x891D + CT 100 → TT (dispatched at scheduled time)
  Frame 0x891D + VL 50  → RC (BAG=4ms, compliant)
  Frame 0x0800          → BE (forwarded in idle slots)

--- Transparent Clock ---
  PCF traversed 3 switches: residence = 2.1 + 3.4 + 1.8 = 7.3µs
  Compensated sync error: 0.12µs

=== RESULTS: 32 passed, 0 failed ===
=== ALL TESTS PASSED ===

References

  • SAE AS6802: Time-Triggered Ethernet (2011)
  • TTTech: "TTE A Time-Triggered Ethernet Standard"
  • NASA/CR-2015-218844: TTE for Spacecraft Applications
  • Steiner, W. "TTEthernet Dataflow Concept" (2010)
  • ARINC 664 Part 7: AFDX Network (for RC traffic comparison)