Domain Deep Dives

Silicon & Embedded Systems

FPGA, ASIC, RTOS, DMA, bootloaders, watchdogs embedded systems interview questions

FPGA & ASIC Design

#	Question	Level
1	Compare FPGA vs ASIC. When would you choose each for a product?	SDE 2
2	Explain timing closure. What do you do when a design doesn't meet timing?	SDE 3
3	How do you handle clock domain crossings (CDC)? What are the failure modes?	SDE 3
4	Describe the FPGA design flow from RTL to bitstream.	SDE 2

DMA & Memory Architecture

#	Question	Level
5	Explain DMA. Why is it critical for high-bandwidth embedded systems?	SDE 2
6	How do you handle cache coherency between CPU and DMA in an ARM system?	SDE 3
7	Explain memory-mapped I/O vs port-mapped I/O. How do you prevent compiler optimization issues?	SDE 2

Interrupts & RTOS

#	Question	Level
8	Explain interrupt latency. How do you minimize it?	SDE 2-3
9	What is priority inversion? Explain the Mars Pathfinder incident.	SDE 2-3
10	Design an ISR for a UART receive buffer. What are the constraints?	SDE 2
11	Compare FreeRTOS vs Zephyr vs Linux RT.	SDE 2-3

Watchdog & Reliability

#	Question	Level
12	Design a watchdog strategy for a safety-critical embedded system.	SDE 3
13	Explain the boot sequence for an embedded Linux device.	SDE 2-3

Low-Power Design

#	Question	Level
14	How do you design a battery-powered IoT sensor to last 5 years on a coin cell?	SDE 3
15	Explain power domains and voltage scaling in modern SoCs.	SDE 3